The present invention relates to a clock alignment training operation required for a semiconductor device operating at high speed as a semiconductor design technology, and more particularly, to a circuit for performing a clock alignment training operation stably even in the semiconductor device operating at higher speed.
A semiconductor device is a device for storing data in a system including a plurality of semiconductor devices. For example, data are required in a data processing device such as a Memory Control Unit (MCU), a semiconductor device outputs data corresponding to an address inputted from a device requiring the data or stores the data supplied from the data requiring device at a position corresponding to the address.
For this, recent memory devices operating at high speed are designed to input/output two data between a rising edge and a falling edge of a system clock applied from outside and to input/output two data between the falling edge and a following rising edge. In short, they are designed to input/output four data in one period of the system clock.
However, since the system clock is represented by only two states, i.e., a logic high level or a logic low level, in order to input/output four data at one period, a data clock having a frequency two times faster than the system clock is required. That is, there is a dedicated clock for inputting/outputting data.
Therefore, the semiconductor device operating at high speed is controlled to allow a data clock to have a frequency twice faster than a system clock by using a system clock as a reference clock while an address and a command are transmitted and received and using a data clock as the reference clock while the data is inputted/outputted.
That is, four data can be inputted/outputted at one period of the system clock by allowing the data clock to repeat two periods at one period of the system clock and to generate the data input/output at a rising edge and a falling edge, respectively.
Like this, differently from a related Double Data Rate (DDR) synchronization memory device using one system clock as a reference to perform operations of reading or writing, the semiconductor device operating at high speed transmits and receives data by using two clocks having frequencies different from each other to perform an operation of reading or writing.
However, if the system clock is not aligned with the data clock, it means that a criterion for transmitting an operation command and an address is not aligned with a criterion for transmitting data and that the semiconductor device operating at high speed does not operate normally.
Accordingly, in order to operate the semiconductor device operating at high speed normally, an operation such as interface training should be performed between the semiconductor device and a data processing device at an initial operation.
Herein, the interface training means a training to operate at a time when an interface for transmitting commands, addresses and data is optimized before a normal operation between the semiconductor device and the data process device is performed.
Such interface training is divided into address training, clock alignment training, a WCK2CK training, a reading training, a writing training and the like. For these trainings, an operation of aligning the data clock and the system clock is performed in the clock alignment training, and the WCK2CK training.
FIG. 1 is a block diagram illustrating a circuit for performing clock alignment training according to a related art.
Firstly, a basic principle of the clock alignment training is explained, the semiconductor device operating at high speed receives an address signal and a command signal from an external controller with reference to a system clock HCK as described above and outputs the data stored inside the semiconductor device with reference to a data clock WCK to the external controller.
Therefore, if a phase difference exists between the system clock HCK and the data clock WCK, the data stored inside the semiconductor device arrives at the external controller slower or faster by the time corresponding to the phase difference.
Therefore, the clock alignment training is an operation for reducing the phase difference between the system clock HCK and the data clock WCK by detecting the phase difference between the system clock HCK and the data clock WCK applied from the external controller at an initial operation of the semiconductor device operating at high speed and transmitting the detection result to the outside controller.
That is, a circuit for performing the clock alignment training according to the related art shown in FIG. 1 is a circuit for performing an operation to receive the system clock HCK and the data clock WCK from the external controller, detect the phase difference therebetween, and transmit the detection result to the external controller.
Referring to FIG. 1, the circuit includes a clock input unit 100, a frequency converting unit 120, a phase detecting unit 140 and a signal transmitting unit 160. The clock input unit 100 receives an external data clock OUT_WCK and an external system clock OUT_HCK to output the system clock HCK for synchronizing input timings of the address signal and the command signal, and the data clock WCK for synchronizing input timings of the data signals from the external controller. The data clock WCK has a frequency higher than that of the system clock HCK.
The frequency converting unit 120 generates a data dividing clock DIV_WCK by dividing a frequency of the data clock WCK in such a manner that the data dividing clock DIV_WCK has the same frequency as that of the system clock HCK. The phase detecting unit 140 detects the phase difference between the system clock HCK and the data dividing clock DIV_WCK and generates a detection signal DET_SIG corresponding to the result. The signal transmitting unit 160 transmits the detection signal DET_SIG to the external controller as a training information signal TRAINING_INFO_SIG.
FIG. 2 is a timing diagram showing an operational waveform of the circuit for performing the clock alignment training according to the related art shown in FIG. 1.
As shown, although the frequency of the data clock WCK inputted into the circuit for performing the clock alignment training according to the related art in the external controller is higher than the frequency of the system clock HCK, since the frequency of the data clock WCK becomes equal to the frequency of the system clock HCK by converting the frequency of the data clock WCK in the frequency converting unit 120, it is noted that the frequency of the data clock DIV_WCK outputted in the frequency converting unit 120 is equal to the frequency of the system clock HCK.
Also, before the clock alignment training operation is started {circle around (1)}, it is noted that a clock edge is not a state of being synchronized with each other. That is, before the clock alignment training operation is started {circle around (1)}, it is noted that the phases of the data clock WCK and the data dividing clock DIV_WCK are not synchronized with that of the system clock HCK.
After the clock alignment training operation is started {circle around (2)}, {circle around (3)}, {circle around (4)}, {circle around (5)} and {circle around (6)}, it is noted that phases of the data clock WCK and the data dividing clock DIV_WCK can be changed at a state of fixing the phase of the system clock as a method for synchronizing the phases of the data clock WCK and the data dividing clock DIV_WCK with the phase of the system clock HCK.
At this time, the phases of the data clock WCK and the data dividing clock DIV_WCK are changed corresponding to a logic level of the training information signal TRAINING_INFO_SIG transmitted to the external controller by the signal transmitting unit 160. That is, since the logic level of the training information signal TRAINING_INFO_SIG is a state of a logic low level continuously, the phases of the data clock WCK and the data dividing clock DIV_WCK are slightly changed to apply the changed phases to a circuit for performing the clock alignment training in the external controller.
Thereafter, at the time of synchronizing the phases between the data clock WCK and the data dividing clock DIV_WCK, and the system clock HCK {circle around (6)}, the logic level of the training information signal TRAINING_INFO_SIG is changed into a logic high level from a logic low level and the phases of the data clock WCK and the data dividing clock DIV_WCK are not changed further in a period {circle around (7)} maintaining such state continuously. In other words, since the logic level of the training information signal TRAINING_INFO_SIG is changed into a logic high level, the phases of the data clock WCK and the data dividing clock DIV_WCK are fixed in the external controller to apply the fixed phases to a circuit for performing the clock alignment training.
Finally, after the circuit for performing the clock alignment training compares the data clock WCK with the system clock HCK in the phase detection unit 140 continuously until the phases of the data clock WCK and the system clock HCK inputted from the external controller are synchronized through the clock alignment training operation, it is noted that the circuit for performing the clock alignment training transmits the comparison result, i.e., the training information signal, TRAINING_INFO_SIG to the external controller.
In this way, seeing a structure of the circuit for performing the clock alignment training according to the related art with reference to FIG. 1, the data clock WCK and the system clock HCK applied through the clock input unit 100 are applied to the phase detecting unit 140 through clock paths different from each other, and the lengths of the clock paths are relatively long.
While the data clock WCK and the system clock HCK pass the relatively long clock paths that are different from each other, there is a problem in that the clock is distorted or disappears by generating noises in any one clock path or all clock paths during the passing.
In case that such a problem occurs, since the result outputted from the phase detecting unit 140 is not reliable, another problem of consuming a relatively a large amount of time occurs due to additional operations such as performing the clock training operation again from the beginning.
The above described problems may occur frequently when the data clock WCK and the system clock HCK are of high frequencies. Consequently, in the semiconductor device operating at higher speed, the clock alignment training operation may not be performed stably.